1. Field of the Invention
The present invention relates to programming an ETOX FLASH or EPROM memory and, more particularly, to a method for programming these memories when cells of the array are formed to store multiple bits of data, i.e., more than a logic "1" and a logic "0".
2. Description of the Related Art
An ETOX array architecture is a type of nonvolatile memory architecture that is characterized by a metal drain line that contacts each drain region in a column of drain regions. The ETOX architecture can be utilized with both U-V erasable EPROMs as well as flash memories.
FIG. 1 shows a portion of a conventional ETOX array 10. As shown in FIG. 1, array 10 includes a plurality of field oxide regions FOX which are arranged in columns and rows, and a series of common source bit lines CSBL1-CSBLm which are arranged so that one row of field oxide regions FOX is formed between each pair of adjacent common source bit lines CSBL1-CSBLm.
A plurality of memory cells 12 and drain regions 14 are also arranged in columns and rows so that a pair of memory cells 12 are formed between each pair of horizontally-adjacent field oxide regions FOX, and so that a drain region 14 is formed between each pair of memory cells 12 that are formed between each pair of horizontally-adjacent field oxide regions FOX.
Array 10 further includes a series of word lines WL1-WLn which are arranged so that one word line WL is formed over each of the memory cells 12 in a row of memory cells 12. As is well known, the portion of the word line WL which is formed over each memory cell 12 functions as the control gate of that memory cell 12.
In addition, a series of metal drain lines MDL1-MDLs are formed so that each metal drain line MDL contacts each of the drain regions 14 in a corresponding column of drain regions 14.
A cell 12 in array 10 is conventionally programmed to store one bit of data by applying an intermediate voltage to the metal drain line MDL that contacts the cell 12 to be programmed, grounding the common source bit lines CSBL1-CSBLm, and applying a programming voltage to the word line WL that corresponds with the cell 12 to be programmed.
For example, to program cell A, an intermediate voltage (approximately 5-7 V) is applied to metal drain line MDL1, while the common source bit lines CSBL1-CSBLm are held at ground. The remaining metal drain lines MDLs are allowed to float or are grounded.
The programming voltage (approximately 12 V) is applied to word line WL1, while the remaining word lines WL2-WLn are grounded. These bias conditions, in turn, cause electrons to be injected from common source bit line CSBL1 to the floating gate of cell A, thus programming cell A.
One drawback to programming memory cells 12 as described above is that only one cell in a column of cells can be programmed at any one time. Although it would appear that multiple cells in a column could be simultaneously programmed by applying the programming voltage to the word lines WL2-WLn that correspond to each cell in the column to be programmed, the high current requirements of each cell during programming (approximately 400 mA) preclude this. Thus, there is a need for a method of programming multiple cells in a column of an ETOX array at the same time.